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GS8150V18AB-333 Datasheet 1m X 18/ 512k X 36 18mb Register-register Late Write Sram

Manufacturer: GSI Technology

Overview: Product Preview GS8150V18/36AB-357/333/300/250 .. 119-Bump BGA mercial Temp Industrial.

This datasheet includes multiple variants, all published together in a single manufacturer document.

General Description

250 MHz–357 MHz 1.8 V VDD 1.5 V or 1.8 V HSTL I/O Because GS8150V18/36A are synchronous devices, address data inputs and read/write control inputs are captured on the rising edge of the input clock.

Write cycles are internally selftimed and initiated by the rising edge of the clock input.

This

Key Features

  • Register-Register Late Write mode, Pipelined Read mode.
  • 1.8 V +150/.
  • 100 mV core power supply.
  • 1.5 V or 1.8 V HSTL Interface.
  • ZQ controlled programmable output drivers.
  • Dual Cycle Deselect.
  • Fully coherent read and write pipelines.
  • Byte write operation (9-bit bytes).
  • Differential HSTL clock inputs, K and K.
  • Asynchronous output enable.
  • Sleep mode via ZZ.
  • IEEE 1149.1 JTAG-compliant Serial Boun.

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